In recent times, Dynamic Random Access Memory (DRAM) has been widely used throughout the world, because information can be freely input to or output from DRAM, and it is capable of being implemented as a high-capacity memory.
Generally, the DRAM is comprised of a metal oxide semiconductor (MOS) transistor and a storage capacitor. The MOS transistor enables charges carrying data to move in the storage capacitor during write and read operations. In addition, DRAM performs a refresh operation that periodically provides charges to the storage capacitor so as to prevent the occurrence of lost or damaged data caused by a leakage current or the like.
In order to produce a highly integrated DRAM, a capacitor is needed that can provide sufficient storage capacity in a smaller area. In order to increase price competitiveness of DRAM, increasing the integration degree is a matter of the highest priority. For this purpose, each DRAM cell may be formed to have a small-sized cell. However, as the semiconductor device is reduced in size, characteristics of the semiconductor device deteriorate because of a short channel effect.
Typically, DRAM fabrication is restricted by a minimum lithography feature size (F) caused by a photolithography process, and the conventional technology requires an area of 8F2 per memory cell. In addition, a conventional transistor has a planar channel region, which limits integration and current aspects.
In order to overcome the above-mentioned limitations, the conventional transistor with a planar channel region has been improved to include three-dimensional (3D) channel regions such as a recessed gate, a fin gate, a buried gate, etc. However, an improved transistor including 3D channel regions also encounters problems when the semiconductor device is scaled down.
In order to resolve these problems, a vertical transistor has been proposed. In the case of a general transistor, high-density source/drain regions are formed at right and left sides of a semiconductor substrate, such that a channel region of the general transistor is formed in a horizontal direction. In contrast, the vertical transistor includes a high-density source/drain region formed in a vertical direction, such that a channel region thereof is formed at upper and lower parts of the semiconductor substrate.
However, in a conventional vertical transistor, which includes a channel region formed of undoped silicon, it is difficult to control voltage in a structures in the semiconductor. Therefore, in a conventional vertical transistor, it is difficult to effectively control various phenomena, such as a punch-through or floating body effect. That is, when the vertical transistor is not operated, gate induced drain leakage (GIDL) occurs or holes are collected in a structure, such that a threshold voltage of the transistor can be reduced, resulting in an increase in a lost current of the transistor. As a result, charges stored in a capacitor are leaked so that data is lost. In addition, in a conventional vertical transistor, it is difficult to form a One Side Contact (OSC) at a sidewall. For example, in order to form a contact at a sidewall, a mask may be used, or tilted ion implantation may be performed. In the case of forming the contact using a mask, difficulties arise not only in overlay adjustment, but also in pattern implementation. In the case of forming the contact by performing tilted ion implantation, a margin of the tilt angle is reduced because the pattern size of the memory cell is greatly reduced, and adjusting energy is difficult because the energy used in such an ion implantation process is already low.